1. Field of the Invention
Embodiments of the present invention relate to a method of forming a chip carrier substrate to prevent warping while maintaining electrical continuity, and a chip carrier formed thereby.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
One exemplary standard for flash memory cards is the so-called SD (Secure Digital) flash memory card. In the past, electronic devices such as SD cards have included an integrated circuit (“IC”) system consisting of several individually packaged ICs each handling different functions, including logic circuits for information processing, memory for storing information, and I/O circuits for information exchange with the outside world. The individually packaged ICs have been mounted separately on a substrate such as a printed circuit board to form the IC system. More recently, system-in-a-package (“SiP”) and multichip modules (“MCM”) have been developed where a plurality of integrated circuit components have been packaged together to provide a complete electronic system in a single package. Typically, an MCM includes a plurality of chips mounted side by side on a substrate and then packaged. An SiP typically includes a plurality of chips, some or all of which may be stacked on a substrate and then packaged.
The substrate on which the die and passive components may be mounted in general includes a rigid or soft dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for integration of the die into an electronic system. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
One surface of a conventional substrate 20 including an etched conductive layer is shown in FIG. 1. The substrate 20 includes a conductance pattern 22 for transferring electrical signals between the various components mounted on the substrate, as well as between the substrate components and the external environment. The conductance pattern may have any number of configurations and occupy various amounts of space on the substrate. In that past it has been recognized that if the conducting layer on a surface of the substrate is completely etched away from the areas not forming part of the conductance pattern, this results in areas of different thermal expansion properties, and a build up of mechanical stresses in the substrate upon heating of the substrate during IC package fabrication. The metal of the conductance pattern tends to expand upon heating, and having some areas with metal and some areas without results is stress generation in the substrate. The same phenomenon was observed where the areas of the conducting layer not forming part of the conducting layer was left completely intact. These stresses tend to warp the substrate. A warped substrate can result in mechanical stresses and cracking of the semiconductor die, either when the semiconductor die is bonded to the substrate, or thereafter.
It is therefore known to etch a so-called dummy pattern on the substrate in areas not used for the conductance pattern. For example, U.S. Pat. No. 6,380,633 to Tsai entitled, “Pattern Layout Structure in Substrate” discloses forming a crosshatch dummy pattern, such as dummy pattern 24 shown in FIG. 1 formed in regions 26, 28, and 30 on substrate 20 not used for conductance pattern 22. Dummy pattern 24 provides improved semiconductor yields by reducing disparate thermal properties between areas on the substrate having a conductance pattern and areas on the substrate which do not.
The inventors of the present invention have further realized that thermal stresses still result when the dummy pattern 24 is laid down in long straight lines. In particular, it has been found that thermal stresses accumulate over a straight segment of a dummy pattern trace, which thermal stresses increase the longer the length of the straight segment. U.S. Pat. No. 6,864,434 to Chang et al. entitled “Warpage-Preventive Circuit Board And Method For Fabricating The Same” discloses a crosshatch dummy pattern as proposed in Tsai, but Chang et al. break up the dummy pattern into a plurality of regions. While Chang et al. represent an improvement over Tsai, Chang et al. still disclose a system of straight line segments on the substrate which result in stress in the substrate. As semiconductor die become thinner and more delicate, it becomes even more important to minimize the stresses within the substrate.
Moreover, another consequence of the breaking the dummy pattern into a plurality of smaller isolated regions as in Chang et al. is that each region becomes electrically isolated from each other region. Thus, if a static or other electrical charge builds in one region, it may not have a path to ground. Accumulation of these charges can damage or ruin a semiconductor package.